1) Field of the Invention
The present invention relates to a clock phase detecting circuit and a clock regenerating circuit each arranged in the receiving unit in multiplex radio equipment.
Generally, the clock regenerating circuit which is used in the receiving unit of multiplex radio equipment is called a BTR (Bit Timing Recovery) circuit. The clock regenerating circuit usually regenerates a clock component based on a signal obtained by demodulating a multilevel orthogonal modulation signal obtained through PSK (Pulse Shift Keying) or QAM (Quadrature Amplitude Modulation) and then supplies it as an operation timing signal for an identifier (e.g. an A/D converter) that mainly identifies received data (signal).
The clock which is regenerated in the clock regenerating circuit must be agreed in phase with a demodulated signal level identifying timing (when the so-called eye-pattern is most opened). However, a change in trunk state due to temperature changes may cause a deviation in phase of a clock pulse.
Hence both a clock phase detecting circuit that can detect a phase deviation with high accuracy and a clock regenerating circuit that adjusts accurately a deviation in phase of the clock detected by the clock phase detecting circuit and then supplies signal identification clocks with high accuracy have been requested.
2) Description of the Related Art
FIG. 60 is a block diagram illustrating the configuration of a clock regenerating circuit arranged in the receiving unit of a general multiplex radio equipment. Referring to FIG. 60, numeral 71 represents an orthogonal detecting unit; 72 and 73 represent A/D converters; 74 represents a transversal equalizer; and 75 represents a clock regenerating circuit.
The orthogonal detecting unit 71 detects a signal (IF (intermediate frequency) signal) obtained by demodulating a multilevel orthogonal modulation signal due to PSK or QAM and then produces two kinds of baseband signals (an Ich signal and a Qch signal) with a different angle of 90° in phase from each other. As shown in FIG. 60, the orthogonal detecting unit 71 is formed of hybrids (H) 711 and 712, phase detectors 713 and 714, roll-off filters 715 and 716; and a local oscillating unit 717.
In the detecting unit 71, the hybrid 711 splits the IF signal input into two components and then sends respectively to the phase detectors 713 and 714. At this time, the local oscillating unit 717 supplies a carrier regenerating signal synchronized in phase with a carrier wave to the hybrid 712. The hybrid 712 splits the carrier regenerating signal into two signal waves with phases different from each other by 90°: one being output to the phase detector 713 and the other being output to the phase detector 714.
As a result, the phase detectors 713 and 714 receive base band signals (an Ich signal and a Qch signal) having phases different from each other by 90°. The A/D converter (identifying unit) 72 receives the Ich signal via the roll-off filter 715 to perform an A/C conversion (signal identification). The A/D converter (identifying unit) 73 receives the Qch signal via the roll-off filter 716 to perform an A/D conversion (signal identification). Thus digital demodulated signals with phases different from each other by 90° are obtained.
The A/D converter 72 converts the Ich signal from the orthogonal detecting unit 71 to a digital demodulated signal by A/D converting at a predetermined signal level. The A/D converter 73 converts the Qch signal from the orthogonal detecting unit 71 to a digital demodulated signal by A/D converting at a predetermined signal level. The transversal equalizer 74 equalizes each the digital demodulated signals from the A/D converters 72 and 73.
The clock regenerating circuit 75 regenerates A/D conversion clocks, of which the timing at which the A/ID  A/D converters 72 and 73 execute an A/D conversion (the so-called eye pattern in fully opened state) matches the phase, from a received signal to be detected by the orthogonal detecting unit 75 and then supplies them respectively to the A/D converters 72 and 73. The clock regenerating circuit 75 is formed of a square detecting unit 76, a filer 77, and a PLL circuit 78. The PLL circuit 78 is formed of a phase detector (PD) 79, a loop filter 80, an amplifier 81 and an oscillating unit 82.
The square detecting unit 76 subjects a signal to be detected by the orthogonal detecting unit 71 to a square detection. The filter 77 filters the output of the square detecting unit 76.
In the PLL circuit 78, the phase detector 79 phase-compares the signal square-detected by the square detecting unit 76 and input through the filter 77 with the A/D conversion clocks output from the oscillating unit 82 for the A/D converters 72 and 73 and then feedbacks the result as a control signal to the oscillating unit 82 via the loop filter 80 and the amplifier 81. As a result, the clock (an A/D conversion clock) following the phase of a signal to be detected by the orthogonal detecting unit 71 can be obtained.
In the clock regenerating circuit 75 having the above-configuration, the A/D conversion clocks for the A/D converters 72 and 73 following the phase in which the eye pattern of a received signal is most opened are regenerated from the signal to be detected by the orthogonal detecting unit 71 and then sent to the A/D converters 72 and 73, respectively. Then each of the A/D converters 72 and 73 can regenerate the receive signal data through an accurate digitalizing process.
The clock regenerating circuit 83 proposed by Japanese Patent Laid-open Publication (Tokukaisyo) No. 63-215235, as shown in FIG. 61, is formed of a phase deviation detection unit 831, a  an infinite phase shifter 832, and an oscillating unit 833. Numeral 81 represents a demodulating unit which demodulates a received signal and 82 represents a data regenerating unit that regenerates a demodulated signal (data) from the demodulating unit. The data regenerating unit 82 consists of an equalizer (EQL) 821 that subjects a demodulated signal to an equalizing process and an identifier (A/D converter) that identifies and encodes (digitalizes) the level of the demodulated signal processed by the equalizer.
In the clock regenerating circuit 83, the phase deviation detecting unit 831 monitors the output signal from the identifier 822 and then detects the deviation between the signal phase of the most suitable identifying timing in the identifier with the phase of the clock (CLK). The infinite phase shifter 832 provides a phase shift to the signal with a fixed frequency from the oscillating unit 833.
In the clock regenerating circuit 83 with the above-mentioned structure, the phase deviation detecting unit 831 detects a change in phase deviation appeared between the timing to be identified by the identifier 822 and the clock (CLK) supplied as an operation timing of the identifier 822, and the infinite phase shifter 832 phase-shifts the output of the oscillating unit 833 synchronous with the change in the phase deviation. Thus the phase deviation is canceled so that the clock matched with the phase of the identification timing can be regenerated certainly.
However, the clock regenerating circuit 75 shown in FIG. 60 regenerates an A/D conversion clock each for the A/D converters 72 and 73 from a signal to be detected by the orthogonal detecting unit 71, or an analog signal, thus tending to be frequently influenced by the trunk status due to temperature changes or the like. As a result, there is a problem in that the A/D conversion timing of each of the A/D converters 72 and 73 can not be agreed with high accuracy with the most suitable timing in which the eye pattern of a received signal is most opened.
As described above, regenerating the A/D conversion clocks from an analog signal leads to the clock regenerating circuit 75 in an analog configuration, as shown in FIG. 60. Hence, there is a problem in that the analog configuration results in a large circuit scale in addition to a large number of manual adjustments.
On the other hand, in the clock regenerating circuit 83 shown in FIG. 61, the phase deviation detecting unit 831 detects a change in phase deviation and the infinite phase shifter 832 phase-shifts the output of the oscillating unit 833 in synchronism with the phase deviation change. Thus the clock agreed with the phase of the identification timing can be certainly regenerated by canceling the phase deviation. However, the phase deviation detecting unit 831 detects a phase deviation with insufficient accuracy rather than high accuracy. Hence there is a problem in that the operation timing of the identifier 822 cannot be completely agreed with the most suitable timing in which the eye-pattern of a received signal is most opened.